The present invention relates generally to a semiconductor memory and more particularly to a semiconductor memory for use in a test of a non-volatile semiconductor memory such as a flash EEPROM.
FIG. 8 shows a structure of a conventional non-volatile semiconductor memory.
A memory cell array 11 of the conventional non-volatile semiconductor memory, though not shown in detail in FIG. 8, comprises a plurality of electrically programmable memory cells arranged in a matrix. A row decoder 12 includes a decode circuit for decoding row address signals and a word line potential control circuit for determining word line potentials. The decode circuit selects, on the basis of row address signals, a word line and memory cells connected to the selected word line for which data erase, write or read is executed. The word line potential control circuit supplies a predetermined potential to a control gate of the memory cells.
A clock generating circuit 13 generates a clock signal OSC for driving the row decoder 12. A sense amplifier/bitline potential control circuit 14, for example, senses data or controls bitline potentials in respective modes of erase, write and read-out.
A column decoder 15 turns on a column select transistor 16 existing on a predetermined select column on the basis of a column address signal, and leads data of the predetermined select column to an input/output buffer 17 or leads data from the input/output buffer 17 to the predetermined select column.
In these years, attention has been paid to a NAND type EEPROM as a non-volatile semiconductor memory. A memory cell array of the NAND type EEPROM comprises a plurality of NAND cells. The NAND cells include a plurality of series-connected memory cells and two select gate transistors connected respectively to both ends of the series circuit of the memory cells.
FIG. 9 shows an example of a structure comprising the memory cell array 11 (shown in detail) of the NAND type EEPROM and the word line potential control circuit (shown by a block) 12-1, 12-2, . . . , of the row decoder (excluding the decode circuit). FIG. 10 shows in detail the word line potential control circuit 12-1, 12-2, . . . , shown in FIG. 9.
The memory cell array 11 comprises a plurality of NAND cell units each including four series-connected memory cells and select gate transistors connected to both ends of the series-circuit of the memory cells. In each cell unit, a select gate transistor is connected to one end of the series circuit on the bitline BLi (i=1 to 4223) side, and similarly another select gate transistor is connected to the other end of the series circuit on the source line (source terminal VS) side.
One block is constituted by 4224 NAND cell units arranged in the row direction (i.e. the direction of extension of word lines). A page is a unit of memory cells permitting simultaneous read/write.
The number of memory cells of each NAND cell unit is not limited to four, and may be eight, 16, etc. In addition, the number of NAND cell units (bitlines) arranged in the row direction is not limited to 4224, and may be, e.g. 2112.
The word line potential control circuits 12-1, 12-2, . . . , are provided for the respective blocks, as shown in FIG. 9. In FIG. 10, signals Pi (i=0 to Np), Qi (I=0 to Nq) and Ri (i=0 to Nr) are block address signals. Only one signal selected from Np+1 signals Pi is set at power supply potential VCC. Only one signal selected from Nq+1 signals Qi is set at power supply potential VCC. Only one signal selected from Nr+1 signals Ri is set at power supply potential VCC. When Np=7, Nq=7 and Nr=15, it is possible to select Np+1.times.Nq+1.times.Nr+1=1024 blocks.
In the word line potential control circuit corresponding to the selected block, all signals Pi, Qi and Ri are set at H (High) level. The signal Pi is input to an n-channel MOS transistor Qn25 and a p-channel MOS transistor Qp5. The signal Qi is input to an n-channel MOS transistor Qn26 and a p-channel MOS transistor Qp6. The signal Ri is input to an n-channel MOS transistor Qn27 and a p-channel MOS transistor Qp7. In the selected block in which all signals Pi, Qi and Ri are at "H" level, an input signal to an inverter I2 is set at "L" level.
In the word line potential control circuit corresponding to the block having a defective memory cell, a fuse F1 is cut off in order to prevent selection of this block. If the fuse F1 is cut off, the input signal level of the inverter I2 is kept at "H" even if all signals Pi, Qi and Ri are at "H". The reason is that the input terminal potential of the inverter I2 is fixed at "H" by the inverter I2 and a p-channel MOS transistor Qp8.
In the word line potential control circuit corresponding to the selected block, an output signal of the inverter I2 is at "H". The output signal of the inverter I2 is delivered to the gates of n-channel MOS transistors (transfer gates) Qn28 to Qn31 via a depletion type n-channel MOS transistor Qnd1.
Thus, a signal GSGD passes through the MOS transistor Qn28 and becomes a signal SGDm. The signal SGDm is applied to the gate of the drain-side (bitline-side) select gate transistor of the selected block. A signal GSGS passes through the MOS transistor Qn31 and becomes a signal SGSm. The signal SGSm is applied to the gate of the source-side select gate transistor of the selected block.
Similarly, signals GWL0 to GWL3 obtained by decoding low address signals pass through MOS transistors Qn29 to Qn30 and become signals WL0m to WL3m. The signals WL0m to WL3m are applied to the gates of the memory cells of each NAND cell of the selected block.
The potentials of the signals GSGD, GSGS and WL0m to WL3m are set at predetermined values in accordance with the respective modes of erase, write and read.
N-channel MOS transistors Qn22 to Qn24, capacitors C1 and C2, an inverter I1 and a NAND logic circuit G1 constitute a circuit for transferring a potential VPPRW, which is higher than power supply potential VCC, to the gates of the n-channel MOS transistors Qn28 to Qn31 of the selected block.
In the word line potential control circuit corresponding to the selected block, a signal Rm is at "H" level. Thus, a high-voltage switch comprising the transistors Qn22 to Qn24, capacitor C1 and NAND logic circuit G1 is positive-feedback-operated by the clock signal OSC, and the gate potentials of MOS transistors Qn28 to Qn31 increase.
In the word line potential control circuit corresponding to a non-selected block, the signal Rm is at "L" level. Thus, if a signal WLGNDB is at "L" level, an output signal of a NOR logic circuit G2 becomes at "H" level and n-channel MOS transistors Qn32 to Qn34 are rendered conductive. As a result, the signals SGDm and signals WL0m to WL3m are set at "L" level (ground potential).
When the voltage VPPRW is to be transferred to the MOS transistors Qn28 to Qn31, the signal BWLHB is set at 0V. The reason is that the depletion type n-channel MOS transistor Qnd1 is able to transmit the power supply potential VCC from its drain to source when its gate is set at power supply potential VCC and is unable to transmit the potential VCC from its drain to source when its gate is at 0V.
The operations of the erase, write and read modes of the NAND type EEPROM are described, for example, in IEEE Journal of Slid-State Circuits, Vol. 30, No. 11, pp. 1157-64, Nov. 1995.
The write-mode operation of the NAND type EEPROM, in particular, will now be described.
FIG. 11 shows operational waveforms in the write mode.
Date write is successively effected in plural memory cells constituting the NAND cell unit, from the source-line-side memory cell M3 to the bitline-side memory cell M0. An increased write voltage VPP (=about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential VM10 (=about 10V) is applied to the control gate of the non-selected memory cell. An intermediate potential, e.g. power supply potential VCC, is applied to the gate of the bitline-side select gate transistor S1. The gate of the source-line-side select gate transistor S2 is set at 0V. A zero voltage ("0" write) or an intermediate potential ("1" write) is applied to the bitline in accordance with data.
At this time, the bitline potential is transmitted to the selected memory cell. At the time of "0" write, a high voltage is applied between the floating gate of the selected memory cell and the substrate and electrons are tunnel-injected from the substrate into the floating gate. Thus, a threshold voltage of the selected memory cell is shifted to the positive side. At the time of "1" write, electrons do not move and the threshold voltage of the selected memory cell does not change.
FIG. 12 shows power supply lines for supplying power supply potentials VCC and VSS to the word line potential control circuits 12-1, 12-2, . . . , of the row decoder 12. FIG. 13 shows operational waveforms in a batch-write test mode.
The cycle T of the clock signal OSC is generally set in a range of from several-ten nsec to one-hundred several-ten nsec. Since the signal Rm (FIG. 10) in the word line potential control circuit corresponding to the non-selected block is at "L" level, the clock signal OSC does not drive the capacitor C1 (FIG. 10). Thus, 0V is applied to the gates of MOS transistors (transfer gates) Qn28 to Qn31 shown in FIG. 10.
In the batch-write test mode, data write is effected in all memory cells at a time. At this time, in all word line potential control circuits, the signal Rm is set at "H" level and the clock signal OSC drives the capacitor C1. The increased potential VPPRW is applied to the gates of the MOS transistors (transfer gates) Qn28 to Qn31 shown in FIG. 10.
In addition, an increased write voltage VPP (=about 20V) is applied to the control gates of all memory cells. An intermediate potential, e.g. a power supply potential VCC, is applied to the gate of the bitline-side select gate transistor, and 0V is applied to the gate of the source-line-side select gate transistor. Besides, 0V ("0" write) is applied to the bitline.
At this time, parasitic resistance R occurs in the power supply lines for supplying power supply potentials VCC and VSS from power supply pads 18 and 19 to the word line potential control circuits 12-1, . . . ,12-n. Consequently, power supply potentials VCC11, . . . ,VCC1n supplied to the word line potential control circuits 12-1, . . . ,12-n are lower than the power supply potential VCC applied to the power supply pad 18. Similarly, power supply potentials VSS11, . . . ,VSS1n are lower than the power supply potential VSS applied to the power supply pad 19.
Accordingly, the capacitors of the word line potential control circuits 12-1, . . . ,12-n are driven at an amplitude between the power supply potential VCCi (i=1 to n) and power supply potential VSSi. This amplitude is less than the normal amplitude (VCC-VSS).
Consequently, the gate potentials of the MOS transistors (transfer gates) Qn28 to Qn31 become lower than the increased potential VPPRW which is to be normally applied. A potential VQQ, which is lower than the predetermined write potential VPP, is applied to all word lines, and a satisfactory batch-write test cannot be performed.